1. Field of the Invention
The invention relates to a flash memory having a NAND (Not AND) type memory cell, and more particularly, relates to a layout structure and a programming of a memory array.
2. Description of Related Art
A NAND type flash memory has a memory cell array in which NAND type strings are formed by a plurality of memory cells connected in series. A typical NAND string includes: a plurality of memory cells connected in series; a bit line select transistor, connected to one end portion of the memory cells in series; and a source line select transistor, connected to another end portion of the memory cells in series. A drain of the bit line select transistor is connected to a bit line, and a source of the source line select transistor is connected to a source line. The bit line select transistor and the source line select transistor are selectively driven through a select gate line during reading, programming or erasing actions (Patent Document 1).
Patent Document 1: Japanese Patent Publication Number 2012-190501.